![]() So when we type make, then, among other things, src1.d file will be generated: o =.d ) # compile and generate dependency info %.o : %.c # use autogenerated dependencies - include $ (OBJS. Src1.c #include "some_header.h" int main ( void ) UPD: as tavainator pointed out at reddit, this one is easy to solve with -MP flag of gcc, so this issue is no longer relevant for me. Still, this is the easiest way that I'm aware of.Ĭhange of compilation flags doesn't cause targets to rebuild We actually end up specifying prerequisites in a recipe. Ok, something that would really work is to add the make invocation to the recipe for every target which depends on mylib, like: We don't want the app target to always get rebuilt. My next idea was to make mylib.a target phony, so that make will get invoked every time (and will be a no-op if no prerequisites changed), but is's also bad since a target which depends on a phony target will be rebuilt every time. We don't want to care about how to build it. But this is really too much work here, in the app's Makefile: we want to just use the lib. We could factor out prerequisites in a third Makefile, specifically and carefully designed for inclusion, and include it in both mylib/Makefile and app/Makefile, and we'll make sure all the paths are correct, etc, etc. ![]() ![]() The obvious problem here is that there are no prerequisites, so make won't be invoked when we change some mylib's sources. We could add a target wich a simple recipe which just invokes make properly: mylib/Makefile, because it has a lot of irrelevant stuff such as unit tests, etc, and we don't want variable names to clash. Now, we have a project app with a separate Makefile, and we want to use mylib.a there, and of course we want it to be up to date. So, among others, there is a rule which looks like: Consider: we have a library mylib, which is a separate project on its own, and it has its own Makefile.
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